Error-correcting code (ECC) protection of dynamic random access memory (DRAM) is traditionally implemented using extra “out-of-band” data bits (e.g., 64 bits of data plus 8 bits of parity). This approach is costly due to the requirement for one or more DRAM components for storing the ECC data and the additional interface input/output (IO) pins.
In addition, bus structures have been found to be unsuitable for some system on chip (SoC) integrated circuits (SoCs). With increases in circuit integration, transactions can become blocked and increased capacity can create signaling problems. In place of a bus structure, a network on chip (NoC) can be used to support data communications between components of the SoC.
A NoC generally includes a collection of switches that route packets from source circuits (“sources”) on the chip to destination circuits (“destinations”) on the chip. The layout of the switches in the chip supports packet transmission from the desired sources to the desired destinations. A packet may traverse multiple switches in transmission from a source to a destination. Each switch can be connected to one or more other switches in the network and routes an input packet to one of the connected switches or to the destination.